A new PLL design for clock management applications

In this paper we describe a novel Phase-Locked Loop (PLL) design for clock management applications. Such PLLs should operate over a wide range of frequencies, have tight constraints on jitter, power consumption and acquisition time, while being dynamically programmable by software means. In addition to the conventional fine tuning loop, the PLL has a coarse tuning loop to control the operating range by varying the number of delay cells in the voltage controlled oscillator (VCO). As a result, the bandwidth is extended while limiting operation to the linear region of the VCO and reducing jitter. Low-power design of the VCO, including length controller is presented. This PLL design also reduces the complexity of dynamic software control by eliminating VCO length adjustment from outside control.